The present invention relates to an address translation apparatus for translating a logical address into a physical address. More specifically, the invention relates to an address translation apparatus adapted to a virtual storage system which deals with a multiplicity of tasks in a microcomputer system.
In the virtual storage system which deals with a multiplicity of tasks in a conventional microcomputer system, checking of memory access privilege for address translation and memory protection plays an important role in the memory management. Here, the address translation is to translate a logical address designated by a task being executed (hereinafter referred to as logical address) into a physical address on a real memory (hereinafter referred to as physical address). Checking of the memory access privilege is to check whether a memory area of the physical address is the one that is specifically allocated to other tasks, i.e., whether the memory area of the physical address is the one that should not be accessed by the task, based upon a memory protection level allocated to the memory area and upon a memory access privilege level allocated to the task. The microcomputers have been employing already an address translation apparatus which is capable of effecting both the address translation and the checking of memory access privilege. This has been discussed, for example, in Computer Design, Vol. 25, No. 19, Oct. 15, 1986, pp. 21-30.
In the conventional address translation apparatus as will be described later in detail, the address translation and the checking of memory access privilege have been carried out sequentially.
According to the conventional art, the time required for obtaining an effective physical address becomes longer than the time required for address translation by a time required for checking the memory access privilege due to the aforementioned sequential operation.